This overview of current verification techniques, either based on logic simulation and formal verification methods, and introduce the inner workings of symbolic simulation. In particular, includes a variety of solutions that utilize the method and parametrization approaches, including quasi-symbolic simulation, symbolic simulation-based cycle, and parameterizations based on intersecting-support decomposition. In structuring this book, author? Hope is to provide interesting reading for many readers of design automation. Chapters 5 and 6 focus on the recent symbolic simulation technique, and the last chapter discusses the key topics that require further research. Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the field of design automation. Highlights: A discussion of the leading hardware verification techniques, including simulation and formal verification solutions important concepts related to the underlying models and algorithms used in the field The latest innovation in the field of symbolic simulation, the use of techniques such as parametric form and nature of the decomposition of Boolean functions Provide insight into the possibilities of new developments in hardware verification