This book is a comprehensive guide to new and Testing VLSI Design-for-Testability techniques that will enable students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital memory, and analog / mixed-signal design. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations / examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System - In Package (SIP) Testing, which is not yet available in the test book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self improvement from digital to memory circuits. * Discussing nanotechnology test trends and future challenges facing the nanometer design; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-nanotubes, and Hybrid Semiconductor / nanowire / Molecular Computing. * Practical problems at the end of each chapter for students.