Standard Functional Verification describe the science of functional verification that applies to any digital hardware system. It also defines a scientific basis for achieving functional closure and show how true functional closure can be measured by the software. This explains how to compare results from different projects and how to assess the risk of functional bugs at tape-out or on any other products critical crossroads. Producers and consumers of silicon IP therefore have a solid framework to communicate requirements and to align expectations effectively and efficiently. Standard Functional Verification is a valuable reference for verification engineers and managers, and also for developers of verification software.