The design of embedded systems warrants a new perspective for two reasons: Firstly, slow and inefficient memory hierarchies have become barriers of energy embedded systems. Therefore, this book discusses a collaborative approach by proposing a new memory hierarchies and software optimization techniques for optimal utilization of the memory hierarchy. Linking memory architecture design with the compilation-aware memory architecture with fast, energy-saving and memory access time is predicted. Evaluation of optimization techniques using real-life standards for a single processor system, multiprocessor system-on-chip (SoC) and to a digital signal processor system, reports a significant reduction in energy consumption and increase system performance. The final chapter covers optimization techniques for applications consisting of several processes that are found in most modern embedded devices. Advanced Memory Optimization Techniques for Low Power Embedded Processorsis designed for researchers, compiler writers and embedded systems designers / architects who want to optimize energy and performance characteristics of the memory subsystem.