It discusses topics like - the policies and mechanisms required for out-of-order processing such as changing the name, reservation station and reorder buffer - optimized for high performance, such as branch prediction, instruction scheduling, and load-store speculation - choice of designs and devices to tolerate additional latency in the processor cache hierarchy of single and double - state-of-the-art multithreading and multiprocessing emphasize single-chip implementation topics are presented as conceptual ideas, with a metric to assess the performance impact, if appropriate, and examples of realization. The authors also provide enough details on the register transfer level so that the reader can appreciate how the design features improve the performance and complexity.